The present invention relates to a protected MOS transistor circuit and, more particularly, to a MOS transistor integrated circuit having a protecting circuit for obviating rupture of the gate oxide of the MOS transistor on the same semiconductor substrate.
It is known that a relatively high voltage supplied to the gate of a MOS transistor becomes a cause of the rupture of a gate oxide. This rupture causes a permanent electrical short between the gate and the substrate on which the MOS transistor is formed.
FIG. 1 shows a conventional input protecting circuit for a MOS transistor integrated circuit. This protecting circuit protects the gate oxide of input MOS transistor 10 of the integrated circuit against rupture due to a surge voltage. For example, in a defect inspection process, the input terminal 12 of the integrated circuit accidentally receives a surge voltage from something charged, for example, to 2000 to 3000 V. Therefore, this protecting circuit is provided in the front stage of input MOS transistor 10.
As shown in FIG. 1, this protecting circuit has resistor 14 connected between the gate of MOS transistor 10 and input terminal 12. Resistor 14 is formed, for example, of a polycrystalline silicon layer formed over a semiconductor substrate through a field oxide film of 0.6 .mu.m interposed therebetween or a diffused layer formed in the substrate and has resistance R. The protecting circuit further has MOS transistor 16 having the same characteristics as MOS transistor 10. The gate of transistor 16 and one end of a current path are connected to power terminal VSS set to a reference potential. The other end of the current path of transistor 16 is connected to junction 18 between resistor 14 and the gate of transistor 10.
A wiring connecting resistor 14 to transistor 10 is insulatively formed on a semiconductor substrate to form a parasitic capacitance C together with the substrate. The resistance R of resistor 14 and the parasitic capacitance C form a time constant circuit of time constant .tau.= CR. The voltage of junction 18, i.e., the gate potential of transistor 10 gradually varies due to the time constant circuit after the surge voltage is supplied to terminal 12. Transistor 16 is rendered conductive when the potential variation arrives at a predetermined level. At this time, a punch-through current or a surface breakdown current flows from junction 18 to power terminal VSS to cause the charge stored in capacitance C to discharge. The voltage variation of the gate of transistor 10 is saturated at sufficiently low level as compared with the peak value of the surge voltage. Thus, the gate oxide of transistor 10 is not applied from the gate with a high electric field to prevent its rupture.
However, the construction of the conventional input protecting circuit is not suitable for further microminiaturization of the MOS transistors of the integrated circuit. The microminiaturization has the undesired effect that it can interfere with the task of bringing the circuit constants of the protecting circuit to suitable values.
FIG. 2 shows an equivalent circuit of the protecting circuit in FIG. 1. Resistor 20 shown in FIG. 2 corresponds to transistor 16 in a conductive state and has spreading resistance Rb. Resistance Rb is specified according to the substrate in which the MOS transistor integrated circuit is formed.
The electric field intensity in the gate oxide of the MOS transistor depends upon the gate voltage of the MOS transistor and the thickness of the gate oxide. It is known that rupture of the gate oxide normally occurs at the electric field intensity higher than 7 or 8 MV/cm. When the gate oxide of transistor 10 is reduced to the thickness, for example, of 0.02 .mu.m to 0.03 .mu.m by microminiaturization, the gate voltage of transistor 10 is limited to 30 V, at the maximum, to avoid rupture of the gate oxide. The gate voltage of transistor 10 in the steady state is ordinarily represented by the following equation (1): EQU VC =(Rb/R +Rb) VO . . . (1)
where VO is a surge voltage applied to input terminal 12.
Since it is not possible to vary the value of resistance Rb when setting the VC under necessary conditions for preventing the gate oxide of transistor 10 from rupturing, resistance R must be increased as compared with that value it would have had before the microminiaturization. However, the increase in resistance R is not preferred, due to the decrease in the response speed when the integrated circuit is operated, and causes the following disadvantages. The voltage drop across resistor 14 increases proportionally to resistance R. Thus, when resistor 14 is formed of a polycrystalline silicon layer, an insulation breakdown might occurs in a field oxide film under the polycrystalline silicon layer. On the other hand, when resistor 14 is formed of a diffused layer, there might also be a junction breakdown between the diffused layer and the semiconductor substrate. Particularly in case of the junction breakdown, it can occur at a voltage drop lower than that in case of the insulation breakdown.
The value of resistance R of resistor 14 which can firmly prevent the gate oxide of transistor 10 from rupturing will be designated. For example, when a surge voltage is 3000 V, spreading resistance Rb is 50 ohms and the gate voltage of transistor 10 is 20 V, resistance R is necessarily 7.45 k.OMEGA. or higher, as per equation (1).
On the other hand, the value of resistance R of resistor 14 which can reliably prevent a field oxide film from insulatively breaking down can be determined. For example, when the upper limit of an applying voltage, capable of holding the electric field intensity between the field oxide films of 0.6 .mu.m less than 7 MV/cm, is 400 V from the MIL standard test, the resistance is necessarily 1 k.OMEGA. or less.
As a result, when resistance R is set to 7.45 k.OMEGA. or higher in order to effectively obviate the rupture of the gate oxide of transistor 10, the field oxide film insulatively breaks down. On the contrary, when resistance R is set to 1 k.OMEGA. or lower in order to reliably prevent the field oxide film from insulatively breaking down, rupture of the gate oxide of transistor 10 occurs. If the voltage of junction 18 in not sufficiently reduced, not only does the possibility of rupture of the gate oxide of transistor 10 occur, but also the surge withstanding voltage of transistor 16 decreases.
FIG. 3 is an equivalent circuit of a testing circuit of MIL standards. This testing circuit has resistor 22 of 1.5 k.OMEGA. and capacitor 24 of 100 pF, which are connected in series between terminal 12 and terminal VSS in the test operation. Capacitor 24 is charged while switch 26 is opened. The charge stored in capacitor 24 is applied as a surge voltage to terminal 12 at the moment that switch 26 is closed. The MIL standards prove a sufficient practical use if the integrated circuit has a surge withstanding voltage of 1200 V.